1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a technique having advantages when applied to semiconductor devices having a silicon-on-insulator (SOI) structure.
2. Description of the Related Art
An SOI technique has been used to achieve lower power consumption and higher-speed operability for semiconductor devices. In cases where integrated circuits(ICs) are manufactured using the SOI technique, ICs are manufactured from SOI wafers.
The SOI wafers have a structure in which a semiconductor layer or a device-forming region, and a substrate are isolated from each other by a thick silicon oxide layer (hereinafter, referred to as a buried oxide layer) or a first insulating layer. When transistors are formed in the semiconductor layer of a SOI wafer, the silicon serving as a channel region and a diffusion region is completely insulated from the substrate by the silicon oxide layer.
A transistor formed in the semiconductor layer of the SOI wafer (hereinafter, referred to as an SOI transistor) undergoes characteristic variations when hot carriers generated at the ON state of the SOI transistor are accumulated in the channel region of the SOI transistor. To reduce the variations, a potential of the channel region needs to be fixed to stabilize the action of the SOI transistor. Since ICs are generally sealed by resin or ceramic, it is difficult to establish electrical connection with the substrate. Accordingly, a technique in which in addition to a bonding to a front surface of a IC, another bonding to a metal plate attached to a back surface of the IC is made to fix the electrical potential of the metal plate from the exterior is sometimes used. Another technique of fixing the electrical potential of substrate is sometimes used, in which the back surface of the IC is fixed mechanically and electrically to a conductive layer in which a potential of a package member is fixed, using a conductive paste.
Unless the potential is fixed from the back surface of the IC, electrical connection from the surface of the SOI wafer to the substrate needs to be established in wafer processing. In general SOI-transistor manufacturing processes, for electrical connection from the front surface of the wafer to the substrate, a contact hole is formed through the buried oxide layer, and a conductive material is buried therein.
The technique in which electrical connection is established from the front surface of the IC to the substrate is, for example, disclosed in JP-A-2004-319853.
However, with the technique described in the foregoing related art and the referenced patent, the contact connected to the substrate fixes the potential to a ground, so that the substrate and a terminal in the circuit which is connected to the ground are connected to each other through a wire or a first metal. The substrate becomes charged by the bias applied to a stage due to chemical-vapor deposition (CVD) or etching treatment or the bias of an electrostatic chuck applied to attract the wafer toward a stage. The generated charge is input to the transistor via the contact connected to the substrate. There is therefore a possibility that characteristics variations of the transistor and degrading of the gate oxide layer are triggered.